Northwest Logic Uses Blue Pearl Software's Analyze to Maximize IP Core Quality
(firmenpresse) - SAN JOSE, CA -- (Marketwire) -- 06/01/12 -- , a leading provider of EDA software which accelerates electronic design implementation, announced today that , Inc., a leading provider of high-performance, easy-to-use, Intellectual Property (IP) cores, uses to maximize the quality of its IP cores.
"We have been using Blue Pearl's Analyze for several years and found it to be very useful in identifying and resolving coding issues. This, in turn, has helped us maximize the quality of our IP Cores. We not only use Analyze internally, but also recommend it to our customers and partners," said Brian Daellenbach, President of Northwest Logic.
"Northwest Logic and Blue Pearl Software share the same focus on maximizing design quality. Analyze is one component of our Blue Pearl Software Suite which is specifically designed to increase our customers' Quality of Results (QoR)," added Shakeel Jeeawoody, VP Marketing, Blue Pearl Software.
Analyze is a part of . It provides functional design analysis to verify properties, methodology standards and design rules. Its benefits include reducing design risk and improving QoR.
Blue Pearl Software Suite accelerates design implementation with its comprehensive RTL analysis, CDC checks and automatic SDC generation. Its Visualization Verification Environment â„¢ and design technology give users immediate feedback for validating automatically generated pre-synthesis longest paths and SDCs, which are used to drive the efficiency of synthesis and place & route tools.
, founded in 1995 and located in Beaverton, Oregon, provides high-performance, silicon-proven, easy-to-use IP cores including high-performance (PCI Express 3.0, 2.1 and 1.1 cores and drivers), (DDR3, DDR2, LPDDR2, Mobile DDR SDRAM; RLDRAM 3, RLDRAM II), and (CSI-2, DSI). These solutions support a full range of platforms including ASICs, Structured ASICs and FPGAs. For additional information, visit or contact .
provides next generation EDA software that uses new and innovative technology to reduce design flow iterations and increase designer productivity early in the digital design flow. checks RTL designs for functional errors and automatically generates comprehensive and accurate Synopsys Design Constraints (SDC) to improve quality of results (QoR) and reduce FPGA and ASIC design risks.
For more information, please visit Blue Pearl Software at .
Acronyms
ASIC: Application Specific Integrated Circuit
CDC: Clock Domain Crossing
EDA: Electronic Design Automation
FPGA: Field Programmable Gate Array
IP: Intellectual Property
QoR: Quality of Results
RTL: Register Transfer Level
SDC: Synopsys Design Constraints
SOC: System on Chip
Visual Verification Environment is a trademark of Blue Pearl Software, Inc.
All other trademarks are property of their respective owners.
Press Contact:
Georgia Marszalek
ValleyPR, LLC for Blue Pearl Software
+1 650 345 7477
Vinitha Seevaratnam
Northwest Logic
+1 503 533 5800 ext. 308
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Datum: 01.06.2012 - 09:47 Uhr
Sprache: Deutsch
News-ID 1120198
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